The trend in integrated circuits (IC) is to form smaller chips that perform sophisticated functions with high speed. This leads to improvements in computer, communication, and consumer electronics equipment. The devices in the ICs are shrunk down to the deep submicron range in ultra large scale integration (ULSI) technology. Accordingly, the number of devices on a single chip has been increased from a thousand to nearly a billion.
However, the accuracy, controllability, and yield of the semiconductor fabricating process is limited. It has been found that conventional processes like lithography and etching are greatly challenged in the manufacture of submicron or smaller feature size devices. The process becomes harder to control and the yield of the products is reduced.
Metallization is the process for forming contacts and interconnections on a semiconductor substrate. The metallization process plays a vital role in forming defect-free connections to ensure the functionality of the circuits. Problems like open connections, undesired shorts, misalignment, leakage, and high resistance contacts are found to cause serious failures in operation of the circuits.
Referring to FIG. 1, a semiconductor substrate 10 having a gate structure 12, and conductive layers 14 and 16 are illustrated. Typically, the gate structure 12 includes a polysilicon layer 12a, a tungsten silicide layer 12b, and a nitride layer 12c. The conductive layers 14 and 16 can be multilevel polysilicon or conductive structures which are generally referred to as poly-2 (the second polysilicon layer) and poly-4 (the fourth polysilicon), respectively. The conductive layer 14 includes a polysilicon layer 14a, a tungsten silicide layer 14b, and a nitride layer 14c. A dielectric layer or oxide layer 18 is used for insulating between devices and connections.
In the metallization process, the dielectric layer 18 is etched to form contact holes to the conducting structures of layers 14, 16, and gate 12. A photoresist layer 20 is formed over the dielectric layer for defining the contact hole openings.
It has been found that the etching process is difficult to control for forming contact holes with different depths and aspect-ratios in the multilevel structures. The etching of contact holes must be stopped at the polysilicon layer 16, the tungsten silicide layer 14b, the tungsten silicide layer 12b, and the substrate 10, respectively. In manufacturing sub-micrometer devices, the depth of the dielectric layer 18 may be upwards of 2 micrometers and the aspect-ratio can easily be more than 5.
FIG. 2 shows the structure of FIG. 1 after a conventional etching process. As seen, it is not unusual for the polysilicon layer 16 to be broken. Further, the etching is stopped on the nitride layers 12c and 14c. This is caused by the polymer regrowth on the nitride which stops the etching process. Finally, the high aspect ratio contact hole to the substrate 10 is difficult to form and the etching is stopped before reaching the substrate 10. Polymer accumulation in the deep hole is thought to be the cause. If the etching process is made stronger to etch the contact hole down to the substrate 10, the "substrate loss" problem may occur and the junction region can be damaged as indicated with the dashed line.
What is needed is a method for solving the over-etching and under-etching problems in forming multilevel contacts.